Fast Fourier Transform (FFT) is a Fast operating algorithm of a Discrete Fourier Transform (DFT) for transforming data in a time domain into the data in an Frequency domain. The FFT is widely used in designs of digital signal processing and high-speed wired and wireless digital communication systems. Cores which are used for performing FFT and inverse FFT operations can be used in an ODFM system. The full name of the OFDM is Orthogonal Frequency Division Multiplexing, which is an orthogonal frequency division multiplexing algorithm for high-speed data transmission. The OFDM is a manner that uses multiple carrier waves to parallel process input data with a high transfer rate into the data having a lower transfer rate and a number thereof being the same to the number of the carrier waves, and the data are carried on the carrier waves to realize the transmission. Because the modulation of said OFDM employs multiple subcarriers, the hardware design thereof becomes difficult due to a number of the subcarriers increasing. Moreover, the orthogonalities between the subcarriers are difficult to maintain, so it is also difficult to design. The OFDM is implemented by a Discrete Fourier Transform (DFT), and the hardware design utilizes the FFT algorithm. A single memory structure for maintaining a smaller size of the hardware and a usage of butterfly operations have be proposed for the FFT processes, which are the most complex part in the OFDM system.
However, as described above, the proposed structure requires more computing cycles; thus, it is difficult to obtain a higher processing speed. Moreover, a drawback of requiring a higher operating frequency also exists. In an Field of high-speed processing requirements, pipeline structures are utilized to solve the drawback and to obtain a higher processing speed. The FFT/IFFT cores with the pipeline structure have manners of MDC (Multi-path Delay Commutator), SDC (Single-path Delay Commutator), SDF (Single-path Delay Feedback), MDF (Multi-path Delay Feedback). A hardware complexity of the whole structure and data throughput are determined depending on the structure of each of the FFT/IFFT cores.
In recent years, structures employing the pipeline structure combining with parallel processing techniques have been proposed to increase the data throughput. In this case, the more number of parallel paths, the data sampling frequency in each path is fewer, but processing units and memory for performing the operations are also increased at the same time. Thus, it causes a significant increase in hardware costs.
Therefore, it is difficult to decide a suitable structure and the parallel structures according to the desired data throughput and the hardware complexity. Moreover, applications of various algorithms that utilize FFT/IFFT operations to improve the performance of the ODFM receiver are constrained due to the limited factor on the hardware.